Integrated semiconductor device and method to make same

ABSTRACT

A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.

PRIORITY INFORMATION

[0001] This application claims priority from provisional applicationSer. No. 60/447,191 filed Feb. 13, 2003, which is incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

[0002] The invention relates to the field of multiple-gate field effecttransistor (FET) and method to fabricate the same, and in particular tofabricating strained-Si multiple-gate FET structures.

[0003] One of the primary challenges of very large scale integration(VLSI) has been the integration of an ever-increasing number of MOSFETdevices within a single chip. This was achieved mainly in the prior artby scaling down the MOSFET device feature size without excessiveshort-channel effects. When the device becomes smaller and smaller,short-channel effects, which are caused by the two-dimensionalelectrostatic charge sharing between the gate and the source/draindiffusion regions, become a serious issue.

[0004] To scale down a MOSFET feature size without excessiveshort-channel effects, multiple-gate MOSFET structures have beendeveloped. Yan, et al., “Scaling the Si MOSFET: From bulk to SOI tobulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992, have shownthat to reduce short-channel effects for 0.05 μm MOSFETs, it isimportant to have a backside-conducting layer present in the structurethat screens the drain field away from the channel. The Yan, et al.results show that double-gated MOSFETs, or MOSFETs with a top gate and abackside ground plane, or in general multiple-gate device, are moreimmune to short-channel effects and hence can be scaled to shorterdimensions than conventional single-gated MOSFETs.

[0005] In all the multiple-gate MOSFETs, there are at least two gateswhich are opposite to each other, one on each side of the channel. Thetwo gates are electrically connected so that they serve to modulate thechannel. Short-channel effects are greatly suppressed in such astructure because the two gates very effectively terminate the drainfield line preventing the drain potential from being felt at the sourceend of the channel. Consequently, the two-dimensional electrostaticcharge sharing between the gate and the source/drain diffusion regionsin a multiple-gate MOSFET is much smaller than that of a conventionalsingle-gated structure of the same channel length.

[0006] Moreover, multiple-gate MOSFET can provide significantperformance advantages over the single gate devices. Variousmultiple-gate processes have been proposed. One promising approach isthe FinFET technology, where silicon “fins” are defined on an insulatorsubstrate, and two gates are made on the both sidewall of the fin. Highperformance FinFET CMOS has been designed using the state of artindustry settings (See Y-K Choi, et al “Nanoscale CMOS spacer FinFET forthe Terabit era,” IEEE, Electron Device Letters, Vol. 23, No. 1, pp23-27, 2002).

[0007] Another multiple-gate technology is formed using the Tri-GateCMOS technology, which utilizes the additional top surface besides thetwo sidewalls (See B. Doyle, et al. “Tri-Gate fully-depleted CMOStransistors: fabrication, design, and layout,” IEEE VLSI Symposium,2003). Other multiple-gate technology includes Ω-gate technology,gate-all-around technology, etc.

[0008] To implement the multiple-gate technology, conventional thin filmSOI wafers are used. Since the multiple-gate devices have very smallchannel dimension, typically less than 100 nm, thus the non-uniformityof the Si film thickness across a SOI wafer will affect the deviceperformance significantly. Thus, the multiple-gate technology requiresvery good film thickness uniformity. However, the conventional methodsfor SOI substrate production typically involve costly processes such ashigh dose ion implantation or wafer bonding. In addition, the SOIsubstrate produced by conventional methods has limitations in filmthickness range and thickness uniformity. There is also nowell-established method to produce strained-Si multiple-gate device inthe prior art. A strained-Si multiple-gate device is able to combine thebenefits of multiple-gate technology and high electron and holemobility. Strained-Si is shown to enhance electron and hole mobilitysignificantly.

SUMMARY OF THE INVENTION

[0009] According to one aspect of the invention, there is provided amultiple-gate FET structure. The multiple-gate FET structure includes asemiconductor substrate. A gate region is formed on the semiconductorsubstrate. The gate region comprises a gate portion and a channelportion. The gate portion has at least two opposite vertical surfacesadjacent to the channel portion. A source region abuts the gate regionat one end, and a drain diffusion region abuts the gate region at theother end.

[0010] According to another aspect of the invention, there is provided amultiple-gate FET structure. The multiple-gate FET structure includes asemiconductor substrate. A gate region is formed on the semiconductorsubstrate. The gate region comprises a gate portion and a channelportion. The gate portion has at two opposite vertical surfaces and onehorizontal top surface adjacent to the channel portion. A source regionabuts the gate region at one end, and a drain diffusion region abuts thegate region at the other end.

[0011] According to another aspect of the invention, there is provided amethod of forming a multiple-gate FET structure. The method includesproviding a semiconductor substrate, and forming a gate region on thesemiconductor substrate. The gate region comprises a gate portion and achannel portion. The gate portion has at least two opposite verticalsurfaces adjacent to the channel portion. Furthermore, the methodincludes forming a source region that abuts the gate region at one endand forming a drain diffusion region abuts the gate region at the otherend.

[0012] According to another aspect of the invention, there is provided amethod of forming a multiple-gate FET structure. The method includesproviding a semiconductor substrate, and forming a gate region on thesemiconductor substrate. The gate region comprises a gate portion and achannel portion. The gate portion has at two opposite vertical surfacesand one horizontal top surface adjacent to the channel portion.Furthermore, the method includes forming a source region that abuts thegate region at one end and forming a drain diffusion region abuts thegate region at the other end.

[0013] According to another aspect of the invention, there is provided adigitalized semiconductor structure that includes a semiconductorsubstrate. A plurality of fin-shaped strips are formed on thesemiconductor substrate. The fin-shaped strips have identical widths andidentical heights and are distributed evenly throughout the entirestructure, with a feature pitch between one another.

[0014] According to another aspect of the invention, there is provided amethod of forming a digitalized semiconductor structure that includes asemiconductor substrate. The method includes forming a plurality offin-shaped strips on the semiconductor substrate. The fin-shaped stripshave identical widths and identical heights and are distributed evenlythroughout the entire structure, with a feature pitch between oneanother.

[0015] According to another aspect of the invention, there is provided amethod of forming a digitalized semiconductor structure that includes asemiconductor substrate. The method includes forming a firstsemiconductor layer on the substrate. A second semiconductor layer isformed on the first layer, and the second semiconductor layer isdifferent from the first semiconductor layer. Also, the method includespatterning the second semiconductor layer into a plurality of fin-shapedstrips. The fin-shaped strips have identical heights, identical widths,and being distributed evenly throughout the entire substrate, with afeature pitch d between one another. Furthermore, the method includesconverting the first semiconductor layer into a buried oxide layer.

[0016] According to another aspect of the invention, there is provided amethod of forming a digitalized semiconductor structure that includes asemiconductor substrate. The method includes forming a firstsemiconductor layer on the substrate. The first semiconductor layer isconverted into a first porous semiconductor layer. The method includesforming a second semiconductor layer on the first porous semiconductorlayer. The second semiconductor layer is patterned into a plurality offin-shaped strips. The fin-shaped strips having identical heights,identical widths, and being distributed evenly throughout the entiresubstrate, with a feature pitch d between one another. Furthermore, themethod includes converting the first porous semiconductor layer into aburied oxide layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIGS. 1A-1B are schematic diagrams illustrating the concept of thedigitalized semiconductor-on-insulator substrate;

[0018]FIGS. 2A-2C are schematic diagrams illustrating a conventional SOIsubstrate and the IC fabrication process on the conventional SOIsubstrate;

[0019]FIGS. 3A-3C are schematic diagrams demonstrating the ICfabrication process on a digitalized semiconductor-on-insulatorsubstrate;

[0020]FIGS. 4A-4B are schematic diagrams illustrating a technique usedto make a source or drain of a FinFET structure using a digitalizedsemiconductor-on-insulator substrate;

[0021]FIGS. 5A-5C are schematic diagrams illustrating a technique toproduce digitalized semiconductor-on-insulator substrates in accordancewith the invention;

[0022]FIGS. 6A-6B are schematic diagrams illustrating another techniqueto produce digitalized semiconductor-on-insulator substrates inaccordance with the invention;

[0023]FIGS. 7A-7E are schematic diagrams illustrating the formation ofvarious digitalized strained-Si fin structures;

[0024]FIGS. 8A-8F are schematic diagrams illustrating a conventional Simultiple-gate FET transistor;

[0025]FIGS. 9A-9C are schematic diagrams illustrating a multiple-gateFET device fabricated directly on a bulk semiconductor substrate having;and

[0026]FIGS. 10A-10C are schematic diagrams illustrating three differentfin-shaped channel region structures used to form strained-materialmultiple-gate devices.

DETAILED DESCRIPTION OF THE INVENTION

[0027] The invention provides a digitalized semiconductor-on-insulatorsubstrate. The advantage of such a digitalizedsemiconductor-on-insulator substrate is two-fold: (1) low wafer cost dueto the starting substrate for the digitalized semiconductor-on-insulatorsubstrate fabrication is bulk substrate instead of insulating substrate,and (2) uniform fin-shaped strips across the entire wafer, as it isdefined by, for example, an epitaxial step and an etch process on a bulkSi wafer which forms the “fins”, instead of by the SOI film. Thedigitalized semiconductor-on-insulator substrate can be used as ageneral substrate for any multiple-gate CMOS IC design. It is analogousto conventional silicon substrates, which can be used for any CMOS ICapplication.

[0028]FIGS. 1A-1B show the concept of a digitalizedsemiconductor-on-insulator substrate 2. In particular, FIG. 1Aillustrates a top view of the substrate 2, and FIG. 1B is across-sectional view of the substrate 2. In the digitalizedsemiconductor-on-insulator substrate 2, isolated semiconductorstructures 4 (or lines) are provided on the insulating substrate 6. Thelines 4 are distributed evenly throughout the wafer, as shown in FIG. 1Aand FIG. 1B. A typical value of pitch d ranges from 10 nm to 500 nm. Inother embodiments, the semiconductor lines 4 are not limited to Si, theymay comprise relaxed-SiGe, relaxed-Ge, strained-Si, strained-SiGe,strained-Ge, SiC, GaN, GaAs or other III-V materials.

[0029] In alternative embodiments, the insulating substrate 6 caninclude any one of the following: a SOI material, a SSOI (strained-Si oninsulator) material, a SGOI (SiGe on insulator) material, astrained-SGOI (strained-SiGe on insulator) material, a GOI (Ge oninsulator) material, a strained-GOI (strained-Ge on insulator) material.

[0030] In comparison, FIGS. 2A-2C show a conventional SOI substrate 8and the IC fabrication process on the conventional SOI substrate 8 inthe prior art. FIG. 2A shows the conventional SOI substrate 8 having acontinuous semiconductor layer 10 on an insulating substrate 12. In theconventional SOI IC fabrication process, customized IC layout design 14is performed, as shown in FIG. 2B. The SOI substrate 8 is then patternedinto desired semiconductor islands 16 according to the IC layout design14, as shown in FIG. 2C. Those islands 16 may not necessarily have evendimensions and are typically not evenly distributed across the wafer. Onthose islands 16, conventional SOI devices are fabricated.

[0031] In contrast, FIGS. 3A-3C show the multiple-gate IC fabricationprocess on a digitalized semiconductor-on-insulator substrate 18, inaccordance with the invention. In the digitalizedsemiconductor-on-insulator substrate 18, the semiconductor lines 20 aredefined before the start of the IC layout design and semiconductordevice fabrication. The substrate 18 has a feature line pitch value d,as shown in FIG. 3A. Then the customized multiple-gate (FinFET orTri-gate) IC layout design 22 is performed, as shown in FIG. 3B. Duringthe layout design, every semiconductor island 23 (corresponding to theFins) in the design is required to have a digitalized value anddigitalized location so that it can fit into the digitalizedsemiconductor-on-insulator substrate 18 where the lines 20 have a pitchof d. This can be easily done since the pitch d is so small (less than afew hundred nm), and any island 23 in the IC layout design can fit intothe digitalized semiconductor-on-insulator substrate 18 by simplyshifting the location by a distance less than the pitch size. The nextstep is to pattern the digitalized semiconductor-on-insulator substrate18 into a desired structure according to the particular IC layout design22, by simply removing part of the lines 20, as shown in FIG. 3C.

[0032] The benefit of the digitalized semiconductor-on-insulatorsubstrate is that the digitalized semiconductor-on-insulator substratecan be produced in large volume without knowing the individualmultiple-gate IC layout design. Therefore, the cost will be low due tothe large volume. It also makes the IC device fabrication simple, sincethe Fin formation is one critical step. It is a general substrate formultiple-gate FET IC application. The requirement is that all thesemiconductor islands on the IC layout have the same width and sameheight. This requirement is naturally met in FinFET or Tri-gate FETtechnology, where all the fins, i.e., lines, have the same dimension.

[0033] Although all the fins of a FinFET or a Tri-gate FET have the samedimensions and are separated from one another with an identical pitch,their source or drain regions typically have larger sizes than thechannel fins, and all the fins join together in the source and drainregion. FIGS. 4A-4B show the technique used to make larger the size ofthe source or drain out of the digitalized semiconductor-on-insulatorsubstrate. FIGS. 4A-4B illustrate the formation of the source/drainregions 26 of FinFET devices. The semiconductor lines (fins) 28 on adigitalized semiconductor-on-insulator substrate are patterned intodesired structure 32 according to the IC layout design, as shown in FIG.4A. Then a semiconductor regrowth step is performed on the source/drainregion 26 to join various lines 28 together, as shown in FIG. 4B. Thiscan be achieved during the conventional raised source/drain epi regrowthstep. The raised source/drain epi regrowth step is a typically performedon thin SOI devices in order to increase the thickness of source/drainareas to facilitate source/drain contact. The lines 28 between thesource/drain region 26 are fins for the FinFET device.

[0034] Note the semiconductor structures discussed herein can becomprised of various materials, such as Si, Ge, SiGe, SiC, GaAs, orother III-V materials, strained or unstrained etc. The typical SOI andFinFET device are made of Si material.

[0035]FIGS. 5A-5C and FIGS. 6A-6B illustrate techniques to producedigitalized semiconductor-on-insulator substrates in accordance with theinvention. This inventive technique provides an approach to producedigitalized semiconductor-on-insulator substrates with uniform layersand structures with desired thicknesses. Moreover, the inventivetechnique produces digitalized semiconductor-on-insulator substrateswithout costly processes, such as high dose ion implantation or waferbonding as in the conventional SOI fabrication.

[0036]FIG. 5A shows a SiGe or Si layer 51 formed on a single crystalsemiconductor substrate 50, which can be a Si substrate or a SiGevirtual substrate, for example. A top layer 52 is formed on the layer51, and can be either a SiGe or Si layer. The top layer 52 can also beconverted into a porous layer. A single crystal device layer 54 ofeither SiGe or Si is then formed on the top layer 50, for example, byusing standard epi techniques. The device layer 54 is then patternedinto digitalized semiconductor lines 56. Selective etching is thenperformed as shown in FIG. 5B. Since the SiGe layer or porous layer 52etches faster, the layer 52 is etched away while the digitalizedsemiconductor lines 56 remain. An insulator material is refilled in thespace area to form a buried insulator layer 58, resulting in adigitalized SOI structure, as shown in FIG. 5C. The presence of theinsulating layer in the structure gives various benefits for the devicefabricated on this structure, such as reduced parasitic capacitor, whichresults in faster circuit speed or lower power consumption, etc.

[0037]FIGS. 6A-6B show another approach to the technique discussed withreference to FIGS. 5A-5C. In particular, FIG. 6A shows a SiGe or Silayer 61 formed on a single crystal semiconductor substrate 60. A toplayer 62 is formed on the layer 61, and can be either a SiGe or Silayer. The top layer 62 can also be converted into porous material inone alternative embodiment. Then a single crystal device layer 64 ofeither SiGe or Si is formed on the top layer 62, for example, by usingstandard epi techniques, as shown in FIG. 6A. The device layer 64 isthen patterned into digitalized semiconductor lines 66. Selectiveoxidation or nitridation is then performed to convert the layer 62 intoinsulator 68. Since the SiGe layer or porous layer 62 oxidizes fasterand since the dimension is very small, the layer 62 converts toinsulator quickly while the digitalized semiconductor lines 66 are stillthere, as shown in FIG. 6B.

[0038] In yet another aspect of the invention, a technique is providedto produce a digitalized strained-Si-on-insulator substrate to be usedwith strained-Si FinFET applications, and a process to producestrained-Si FinFET devices.

[0039]FIGS. 7A-7E illustrate the formation of a digitalized strained-SiFin structures. In particular, FIG. 7A shows a digitalizedrelaxed-SiGe-on-insulator substrate 70 having SiGe relaxed digitizedstructures or lines 72 and insulating substrate 71. Epi strained-Silayers 74 are grown on the sidewalls of the SiGe lines 72 on thesubstrate 70, as shown in FIG. 7B. Strained-Si FinFET devices can bethen made on this substrate 70. Note the epi strained-Si layers 74 canalso be grown before the step of forming the insulator layer, asdiscussed in FIGS. 5A-5C and FIGS. 6A-6C, but after patterning the SiGelayer into digitalized lines.

[0040]FIG. 7C illustrate another embodiment of a digitalized strained-Sifin structure, where epi strained-Si layers 75 are not only grown on thetwo sidewalls of the SiGe lines 72 on the substrate 70, but also on thetop surface of SiGe lines 72.

[0041]FIGS. 7D-7E illustrate yet another embodiment of a digitalizedstrained-Si fin structure 76. It starts with a uniform strained-Si layer79 on the substrate 70, as shown in FIG. 7D. The layer 79 is thenpatterned into digitalized lines 78, as shown in FIG. 7E. Theembodiments shown in FIGS. 7A-7E of strained-Si substrates havedifferent directions of strain. In the above structure 76, the lines 78can be other materials, such Ge, SiGe, SiC, strained or unstrained.

[0042]FIG. 8A show a conventional Si multiple-gate FET transistor 100,fabricated on a SOI substrate 102. FIG. 8B shows the top view of aconventional Si FinFET or a conventional Si Tri-gate FET 100. FIG. 8Cand FIG. 8D show the cross-section views of the same device 100 in twodifferent directions. The conventional Si FinFET or Tri-gate device 100has several separate Si channel regions 104 (fin-shaped) in between asource region 106 and drain region 108. The fin-shaped channel 104typically has small heights. In order to have a good contact onsource/drain regions, 106, 108 a typical raised source/drain epiregrowth step is used to increase the heights of the source/drainregions 106, 108. The FinFET and Tri-Gate FET devices in the prior artdiffer in the number of gates.

[0043]FIGS. 8E-8F illustrate the detailed structures of the FinFET andTri-gate device, in particular the MOSFET device. FIG. 8E illustrates agate region 80 on the substrate 77. The gate region 80 includes twoportions: a gate portion 82 and a channel portion 84, which includes oneof the line structures 104 from FIG. 8A-8D. The gate portion 82 includestwo opposite gate conductors 86 adjacent to a channel portion 84 andinsulating film 90. The gate conductors 86 can be semiconductor or metalmaterials. The insulating film 90 can be a silicon oxide, nitride orhigh-k dielectric material, such as HfO₂, ZrO₂, Hfn. The source/draindiffusion regions abut the gate region 80, and have junctions connectingto the two ends of the channel portion 84. FIG. 8F shows the gatestructure 92 of a Tri-gate FET. It is similar to the structure 75 shownin FIG. 8E, except the gate conductor 94 of the structure 92 shown inFIG. 8F includes a horizontal top portion 96.

[0044] In order to make the multiple-gate devices on a SOI wafer havingcontrollable performance, the uniformity of the height of all channelstrips across the entire wafer, which originates from the uniformity ofthe starting SOI wafer, is very crucial. Multiple-gate device alsorequire to start with ultra-thin SOI wafers. However, the conventionalmethods for SOI substrate production have limitations in film thicknessand thickness uniformity. The conventional methods also typicallyinvolve costly processes such as high dose ion implantation or waferbonding.

[0045] The invention provides a multiple-gate FET device structure whichdoes not require SOI substrates, and provides much improved fin filmthickness uniformity. FIG. 9A shows the top view of the multiple-gateFET device. FIGS. 9B and 9C show the cross-section view in Y-Y and X-Xdirections respectively. This inventive multiple-gate FET device 110 isfabricated directly on a bulk Si substrate 112 having a source 116 anddrain 118. Note the substrate 112 can also be a SiGe substrate or thelike in other embodiments. Thanks to the multiple-gate structure, thefin-shaped channel regions 114 maintain the same device performance asthose made on an insulating substrate 102. In one embodiment, thesubstrate 112 beneath the fin-shaped channel region 114 is doped suchthat it never turns on, therefore minimizes the influence of the bulksemiconductor substrate on the device performance.

[0046] The difference between this structure and the conventionalmultiple-gate FET in FIG. 8 is the substrate, i.e. bulk Si substrate inFIG. 9 versus insulating substrate in FIG. 8. The advantage of such amultiple-gate FET 110 on bulk substrate 112 is three-fold: (1) low wafercost due to the use of bulk substrate 112 instead of an insulatingsubstrate, (2) uniform fin-shaped strip height across the entire wafer,as it is defined by etch process which forms the fins, and (3) nofloating-body effect since it is not a SOI structure.

[0047] The invention also provides a high mobility multiple-gate FETdevice structure. By using strained-semiconductor materials or high Gecontent materials such as strained-Si, strained-SiGe, or strained-Ge,the device's electron and hole mobility are improved dramatically.However, the use of strained-material is not straightforward. FIGS.10A-10C show three different fin-shaped channel region structures usedto form strained-material multiple-gate devices, using tensilestrained-Si as an example. In FIG. 10A, the fin strip 120 is formeddirectly from a strained-Si on insulator (SSOI) substrate 122. The finstrip 120 has 3 surfaces 124, 126, 128. As indicated in the FIG. 10A,the top horizontal surface 124 exhibit a biaxial tensile strain in bothX and Y directions. The other two vertical surfaces, 126, 128, however,exhibit uniaxial tensile strain, i.e. tensile strain in Y directiononly. In the Z direction, it is compressive strain. As understood in theprior art, biaxial tensile strained-Si shows better mobility enhancementthan uniaxial strained-Si.

[0048]FIG. 10B shows another structure 130. In this structure 130, arelaxed SiGe strip 132 is formed first on a substrate 134. Then astrained-Si regrowth can be performed to form strained-Si films on thetwo vertical surfaces 136, 138 of the relaxed-SiGe strips 132. As aresult, both strained-Si films on the two vertical surfaces 136, 138 arein biaxial tensile strain, in both Y and Z directions. This is amultiple-gate device with the gate portion structure same as the oneshown in FIG. 8E (FinFET). If strained-Si is also deposited on the tophorizontal surface 140 in FIG. 10B, it is also biaxial strained, in bothX and Y direction, as shown in FIG. 10C. This is a multiple-gate devicewith the gate portion structure same as the one shown in FIG. 8F(Tri-gate FET). In other embodiments, other strained-materials, such asstrained-SiGe or strained-Ge, can be used. In these structures, thesubstrate 122 and 134 can be either an insulating substrate, like theone in FIG. 8, or a bulk semiconductor substrate, like the one in FIG.9.

[0049] Although the present invention has been shown and described withrespect to several preferred embodiments thereof, various changes,omissions and additions to the form and detail thereof, may be madetherein, without departing from the spirit and scope of the invention.

What is claimed is:
 1. A multiple-gate field effect transistor (FET)structure comprising: a semiconductor substrate, a gate region formed onsaid semiconductor substrate, said gate region comprising a gate portionand a channel portion, said gate portion having at least two oppositevertical surfaces adjacent to the channel portion; a source regionabutting said gate region at one end; and a drain diffusion regionabutting said gate region at the other end.
 2. The multiple-gate FETstructure of claim 1, wherein said channel portion comprises either a Sichannel, a strained-Si channel, a relaxed-SiGe channel, a strained-SiGechannel, a relaxed-Ge channel, a strained-Ge channel, a SiC channel, aGaN channel a GaAs channel, or other III-V material channel.
 3. Themultiple-gate FET structure of claim 1, wherein said channel portioncomprises a center relaxed-semiconductor material region and an outerstrained-semiconductor material region that covers at least the twoopposite vertical surfaces of the center relaxed-semiconductor materialregion, and said semiconductor substrate comprises Si, SiGe, SiC, Ge,GaN, GaAs or other III-V materials.
 4. The multiple-gate FET structureof claim 3, wherein said center relaxed-semiconductor material is eithera relaxed-Si, a relaxed-SiGe, or a relaxed-SiC, and said outerstrained-semiconductor material comprises either strained-Si,strained-SiGe, strained-SiC or strained-Ge material.
 5. Themultiple-gate FET structure of claim 1, wherein said semiconductorsubstrate comprises a bulk semiconductor substrate, such as a bulk Sisubstrate, a bulk Ge substrate, a bulk SiGe virtual substrate, a bulkGaAs substrate.
 6. The multiple-gate FET structure of claim 1, whereinsaid semiconductor substrate comprises an insulating substrate.
 7. Themultiple-gate FET structure of claim 6, wherein said insulatingsubstrate comprises an insulating layer of one of the followingmaterial: an SOI material, an SSOI (strained-Si on insulator) material,an SGOI (SiGe on insulator) material, a strained-SGOI (strained-SiGe oninsulator) material, a GOI (Ge on insulator) material, or a strained-GOI(strained-Ge on insulator) material.
 8. The multiple-gate FET structureof claim 1, wherein said gate portion further comprises a conductingmaterial film and an insulating film, said insulating film having atleast two opposite vertical surfaces adjacent to the channel regions andseparating said gate conductor from said channel portion.
 9. Themultiple-gate FET structure of claim 1, wherein said gate portioncomprises a poly Si material, or a metal-gate material such as TiN, Mo,Ti.
 10. The multiple-gate FET structure of claim 8, wherein saidinsulating film comprises a high-k dielectric material.
 11. Themultiple-gate FET structure of claim 1, wherein said high-k dielectricmaterial comprises HfO₂, ZrO₂, HfN.
 12. A multiple-gate field effecttransistor (FET) structure comprising: a semiconductor substrate, a gateregion formed on said semiconductor substrate, said gate regioncomprising a gate portion and a channel portion, said gate portionhaving at two opposite verticals surface and one horizontal top surfaceadjacent to the channel portion; and a source region abutting said gateregion at one end; and a drain diffusion region abutting said gateregion at the other end.
 13. The multiple-gate FET structure of claim12, wherein said channel portion comprises either a Si channel, astrained-Si channel, a relaxed-SiGe channel, a strained-SiGe channel, arelaxed-Ge channel, a strained-Ge channel, a SiC channel, a GaN channelor other III-V materials.
 14. The multiple-gate FET structure of claim12, wherein said channel portion comprises a centerrelaxed-semiconductor material region and an outerstrained-semiconductor material region that covers at least the twoopposite vertical surfaces of the center relaxed-semiconductor materialregion.
 15. The multiple-gate FET structure of claim 14, wherein saidcenter relaxed-semiconductor material is either a relaxed-Si, arelaxed-SiGe, or a relaxed-SiC, and said outer strained-semiconductormaterial comprises either strained-Si, strained-SiGe, strained-SiC orstrained-Ge material, and said semiconductor substrate comprises Si,SiGe, SiC, Ge, GaN, GaAs or other III-V materials.
 16. The multiple-gateFET structure of claim 12, wherein said semiconductor substratecomprises a bulk semiconductor substrate, such as a bulk Si substrate, abulk Ge substrate, a bulk SiGe virtual substrate, a bulk GaAs substrate.17. The multiple-gate FET structure of claim 12, wherein saidsemiconductor substrate comprises an insulating substrate.
 18. Themultiple-gate FET structure of claim 17, wherein said insulatingsubstrate comprises an insulating layer of one of the followingmaterial: an SOI material, an SSOI (strained-Si on insulator) material,an SGOI (SiGe on insulator) material, a strained-SGOI (strained-SiGe oninsulator) material, a GOI (Ge on insulator) material, or a strained-GOI(strained-Ge on insulator) material.
 19. The multiple-gate FET structureof claim 12, wherein said gate portion further comprises a conductingmaterial film and an insulating film, said insulating film having atleast two opposite vertical surfaces adjacent to the channel regions andseparating said gate conductor from said channel portion.
 20. Themultiple-gate FET structure of claim 12, wherein said gate portioncomprises or a poly Si material a metal-gate material such as TiN, Mo,Ti.
 21. The multiple-gate FET structure of claim 19, wherein saidinsulating film comprises a high-k dielectric material.
 22. Themultiple-gate FET structure of claim 21, wherein said high-k dielectricmaterial comprises HfO₂, ZrO₂, Hfn.
 23. A digitalized semiconductorstructure comprising: a semiconductor substrate; and a plurality offin-shaped strips formed on said semiconductor substrate, saidfin-shaped strips having identical widths and identical heights andbeing distributed evenly throughout the entire substrate, with a featurepitch d between one another.
 24. The digitalized semiconductor structureof claim 23, wherein each of said fin-shaped strips comprises a widthand a height ranging between 1 nm and 200 nm.
 25. The digitalizedsemiconductor structure of claim 23, wherein said pitch d comprises arange between 5 nm and 500 nm.
 26. The digitalized semiconductorstructure of claim 23, wherein said semiconductor substrate comprises abulk semiconductor substrate, such as a bulk Si substrate, a bulk Gesubstrate, a bulk SiGe virtual substrate, a bulk GaAs substrate.
 27. Thedigitalized semiconductor structure of claim 23, wherein saidsemiconductor substrate comprises an insulating substrate.
 28. Thedigitalized semiconductor structure of claim 27, wherein said insulatingsubstrate comprises an insulating layer of one of the followingmaterial: an SOI material, an SSOI (strained-Si on insulator) material,an SGOI (SiGe on insulator) material, a strained-SGOI (strained-SiGe oninsulator) material, a GOI (Ge on insulator) material, or a strained-GOI(strained-Ge on insulator) material.
 29. The digitalized semiconductorstructure of claim 23, wherein said fin-shaped strips comprise eitherSi, strained-Si, relaxed-SiGe, strained-SiGe, relaxed-Ge, strained-Ge,SiC, GaN, GaAs, other III-V materials, or a semiconductor comprising ofmore than one material.
 30. The digitalized semiconductor structure ofclaim 31, wherein said semiconductor comprises a centerrelaxed-semiconductor material region and an outerstrained-semiconductor material region that covers at least the twoopposite vertical surfaces of the center relaxed-semiconductor materialregion.
 31. The digitalized semiconductor structure of claim 30, whereinsaid center relaxed-semiconductor material is either a relaxed-Si, arelaxed-SiGe, or a relaxed-SiC, GaN, GaAs, other III-V materials andsaid outer strained-material comprises either strained-Si,strained-SiGe, strained-SiC, or strained-Ge material.
 32. Thedigitalized semiconductor structure of claim 30, wherein said outerstrained-semiconductor material region further covers the horizontal topsurfaces of the center relaxed-semiconductor material region.
 33. Amethod of forming a multiple-gate field effect transistor (FET)structure comprising comprising: providing a semiconductor substrate,forming a gate region formed on said semiconductor substrate, said gateregion comprising a gate portion and a channel portion, said gateportion having at least two opposite vertical surfaces adjacent to thechannel portion; forming a source region abutting said gate region atone end; and forming a drain diffusion region abutting said gate regionat the other end.
 34. The method of claim 33, wherein said channelportion comprises either a Si channel, a strained-Si channel, arelaxed-SiGe channel, a strained-SiGe channel, a relaxed-Ge channel, astrained-Ge channel, or a SiC channel.
 35. The method of claim 33,wherein said channel portion comprises a center relaxed-semiconductormaterial region and an outer strained-semiconductor material region thatcovers at least the two opposite vertical surfaces of the centerrelaxed-semiconductor material region.
 36. The method of claim 35,wherein said center relaxed-semiconductor material is either arelaxed-Si, a relaxed-SiGe, or a relaxed-SiC, and said outerstrained-semiconductor material comprises either strained-Si,strained-SiGe, strained-SiC or strained-Ge material, and saidsemiconductor substrate comprises Si, SiGe, SiC, Ge, GaN, GaAs or otherIII-V materials.
 37. The method of claim 33, wherein said semiconductorsubstrate comprises a bulk Si substrate.
 38. The method of claim 34,wherein said semiconductor substrate comprises an insulating substrate.39. The method of claim 38, wherein said insulating substrate comprisesan insulating layer of one of the following material: an SOI material,an SSOI (strained-Si on insulator) material, an SGOI (SiGe on insulator)material, a strained-SGOI (strained-SiGe on insulator) material, a GOI(Ge on insulator) material, or a strained-GOI (strained-Ge on insulator)material.
 40. The method of claim 33, wherein said gate portion furthercomprises a conducting material film and an insulating film, saidinsulating film having at least two opposite vertical surfaces adjacentto the channel regions and separating said gate conductor from saidchannel portion.
 41. The method of claim 33, wherein said gate portioncomprises a metal-gate material.
 42. The multiple-gate FET structure ofclaim 41, wherein said insulating film comprises a high-k dielectricmaterial.
 43. The method of claim 33, wherein said high-k dielectricmaterial comprises HfO.
 44. A method of forming a multiple-gate fieldeffect transistor (FET) structure comprising: providing a semiconductorsubstrate, forming a gate region formed on said semiconductor substrate,said gate region comprising a gate portion and a channel portion, saidgate portion having at two opposite vertical surface and one horizontaltop surface adjacent to the channel portion; and forming a source regionabutting said gate region at one end; and forming a drain diffusionregion abutting said gate region at the other end.
 45. The method ofclaim 44, wherein said channel portion comprises either a Si channel, astrained-Si channel, a relaxed-SiGe channel, a strained-SiGe channel, arelaxed-Ge channel, a strained-Ge channel, or a SiC channel.
 46. Themethod of claim 44, wherein said channel portion comprises a centerrelaxed-semiconductor material region and an outerstrained-semiconductor material region that covers at least the twoopposite vertical surfaces of the center relaxed-semiconductor materialregion.
 47. The method of claim 46, wherein said centerrelaxed-semiconductor material is either a relaxed-Si, a relaxed-SiGe,or a relaxed-SiC, and said outer strained-semiconductor materialcomprises either strained-Si, strained-SiGe, strained-SiC or strained-Gematerial, and said semiconductor substrate comprises Si, SiGe, SiC, Ge,GaN, GaAs or other III-V materials.
 48. The method of claim 44, whereinsaid semiconductor substrate comprises a bulk Si substrate.
 49. Themethod of claim 44, wherein said semiconductor substrate comprises aninsulating substrate.
 50. The method of claim 49, wherein saidinsulating substrate comprises an insulating layer of one of thefollowing material: an SOI material, an SSOI (strained-Si on insulator)material, an SGOI (SiGe on insulator) material, a strained-SGOI(strained-SiGe on insulator) material, a GOI (Ge on insulator) material,or a strained-GOI (strained-Ge on insulator) material.
 51. The method ofclaim 44, wherein said gate portion further comprises a conductingmaterial film and an insulating film, said insulating film having atleast two opposite vertical surfaces adjacent to the channel regions andseparating said gate conductor from said channel portion.
 52. The methodof claim 44, wherein said gate portion comprises a metal-gate material.53. The method of claim 51, wherein said insulating film comprises ahigh-k dielectric material.
 54. A method of forming a digitalizedsemiconductor structure comprising: providing a semiconductor substrate;and forming a plurality of fin-shaped strips formed on saidsemiconductor substrate, said fin-shaped strips having identical widthsand identical heights and being distributed evenly throughout the entiresubstrate, with a feature pitch d between one another.
 55. The method ofclaim 54, wherein each of said fin-shaped strips comprises a width and aheight ranging between 1 nm and 200 nm.
 56. The method of claim 54,wherein said pitch d comprises a range between 5 nm and 500 nm.
 57. Themethod of claim 54, wherein said semiconductor substrate comprises abulk Si substrate.
 58. The method of claim 54, wherein saidsemiconductor substrate comprises an insulating substrate.
 59. Themethod of claim 58, wherein said insulating substrate comprises aninsulating layer of one of the following material: an SOI material, anSSOI (strained-Si on insulator) material, an SGOI (SiGe on insulator)material, a strained-SGOI (strained-SiGe on insulator) material, a GOI(Ge on insulator) material, or a strained-GOI (strained-Ge on insulator)material.
 60. The method of claim 54, wherein said fin-shaped stripscomprise either Si, strained-Si, relaxed-SiGe, strained-SiGe,relaxed-Ge, strained-Ge, SiC, or a semiconductor comprising of more thanone material.
 61. The method of claim 60, wherein said semiconductorcomprises a center relaxed-semiconductor material region and an outerstrained-semiconductor material region that covers at least the twoopposite vertical surfaces of the center relaxed-semiconductor materialregion.
 62. The method of claim 61, wherein said centerrelaxed-semiconductor material comprises either a relaxed-Si, arelaxed-SiGe, or a relaxed-SiC, and said outer strained-materialcomprises either strained-Si, strained-SiGe, strained-SiC or strained-Gematerial.
 63. The method of claim 61, wherein said outerstrained-semiconductor material region further covers the horizontal topsurfaces of the center relaxed-semiconductor material region.
 64. Amethod of forming a digitalized semiconductor structure comprising:providing a semiconductor substrate; forming a first semiconductor layeron said substrate; forming a second semiconductor layer on said firstsemiconductor layer, and said second semiconductor layer is differentfrom said first semiconductor layer; patterning said secondsemiconductor layer into a plurality of fin-shaped strips, saidfin-shaped strips having identical heights, identical widths, and beingdistributed evenly throughout the entire substrate, with a feature pitchd between one another; and converting said first semiconductor layerinto a buried oxide layer.
 65. The method of claim 64, wherein saidsemiconductor substrate comprises a Si substrate, or a SiGe virtualsubstrate with a relaxed SiGe film on a top layer.
 66. The method ofclaim 64, wherein said first layer comprises either a Si layer, astrained-Si layer, a relaxed-SiGe layer, a strained-SiGe layer, arelaxed-Ge layer, a strained-Ge layer, or a SiC layer.
 67. The method ofclaim 64, wherein said second layer comprises either a Si layer, astrained-Si layer, a relaxed-SiGe layer, a strained-SiGe layer, arelaxed-Ge layer, a strained-Ge layer, or a SiC layer, and said firstlayer is different from said second layer by different material or bydifferent doping type.
 68. The method of claim 64, wherein said firstlayer comprises a faster oxidation or nitridation rate than the secondlayer, and said first layer is converted into a buried oxide layer byselectively oxidation or nitridation.
 69. The method in claim 64,wherein said first layer comprises faster etch rate than the secondlayer, and said first layer is converted into a buried oxide layer byselectively etching away the first layer and then the empty spaces arefill with insulator.
 70. The method of claim 64 further comprisingforming multiple-gate FET devices on the structure.
 71. A method offorming a digitalized semiconductor structure comprising: providing asemiconductor substrate; forming a first semiconductor layer on saidsubstrate; converting said first semiconductor layer into a first poroussemiconductor layer; forming a second semiconductor layer on said firstporous semiconductor layer; patterning said second semiconductor layerinto a plurality of fin-shaped strips, said fin-shaped strips havingidentical heights, identical widths, and being distributed evenlythroughout the entire substrate, with a feature pitch d between oneanother; and converting said first porous semiconductor layer into aburied oxide layer.
 72. The method of claim 71, wherein saidsemiconductor substrate comprises a Si substrate or a SiGe virtualsubstrate with a relaxed SiGe film on a top layer.
 73. The method ofclaim 71, wherein said first layer comprises either a Si layer, astrained-Si layer, a relaxed-SiGe layer, a strained-SiGe layer, arelaxed-Ge layer, a strained-Ge layer, or a SiC layer.
 74. The method ofclaim 71, wherein said second layer comprises either a Si layer, astrained-Si layer, a relaxed-SiGe layer, a strained-SiGe layer, arelaxed-Ge layer, a strained-Ge layer, or a SiC layer.
 75. The method inclaim 71, wherein said first porous semiconductor layer is convertedinto a buried oxide layer by selectively oxidizing said first porouslayer.
 76. The method in claim 71 wherein said first poroussemiconductor layer is converted into a buried oxide layer byselectively etching away said first porous layer and then the emptyspaces are filled with oxide. 77 The method in claim 71 furthercomprising forming multiple-gate FET devices on the structure.